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31710hkim 20091215-s00006 no.a1647-1/37 LC74950BG overview the LC74950BG is an analog display i/f ic that converts analog video signals into equivalent digital video signals. it incorporates 3 channels of adc and a pll circuit. features ? maximum sampling frequency: 40msps ? 8-bit output ? supports self-clamp (bottom/center switching) and digital clamp ? input signal: 1.0vp-p maximum ? external clock input ? low jitter pll ? power down mode ? low power consumption ? input format: supports rgb and ycbcr ? built-in i 2 c bus interface lsi specifications ? supply voltage core: 1.5 10% i/o: 3.3v 0.3v (40mhz) or 2.4v to 3.6v (30mhz) ? maximum operating frequency: 40mhz ? package: fbga96 principal applications ? small-size monitors ordering number : ena1647 cmos ic silicon gate 40/30msps analog display i/f lsi specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC74950BG no.a1647-2/37 functions & overview 1. input all the inputs listed below can be connected to the analog ports. it is also possible to switch between the inputs of two systems and use the one selected. ycbcr/ypbpr input (480i/576i, 480p/576p): component input rgb: rgb input external clock supported 2. output digital 8-bit/channel output 3. clamp analog clamping and digital clamping supported 4. gain digital gain adjustment 5. pll circuit this circuit can be used as the h lock or frequency-multiplied clock. it is also possible to use the pll circuit and analog-digital converter (adc) independently. h lock pll circuit: this makes it possible to generate a clock synchronized with the external h sync signal. frequency-multiplier pll circuit: this makes it possible to ge nerate clocks synchronized with an external clock. 6. external interface i 2 c: this supports the 100khz mode. it is possible to select slave addresses by establishing pin settings. slave addresses: 0x98, 0x9a 7. pdown power-down of the whole system can be controlled using the pdown pin. alternatively, the adc, pll and other circuits can be powered down separately using register settings. this makes it possible to limit the power as required. specifications absolute maximum ratings at ta = 25 c, dv ss = 0v, av ss = 0v parameter symbol conditions ratings unit maximum supply voltage (i/o) dv dd 33 av dd 33 -0.3 to +3.95 v maximum supply voltage (core) dv dd 15 av dd 15 -0.3 to +1.8 v v i -0.3 to +5.5 v digital input voltage v i (when in low voltage) -0.3 to dv dd 33+0.3 v digital output voltage v o -0.3 to dv dd 33+0.3 v operating temperature topr -30 to +70 c storage temperature tstg -55 to +125 c allowable operating ranges at ta = -30 to +70 c ratings parameter symbol conditions min typ max unit av dd 33 3.00 3.3 3.60 v max 40mhz 3.00 3.3 3.60 v supply voltage (i/o) dv dd 33 max 30mhz 2.40 3.3 3.60 v supply voltage (i/o) dv dd 15 av dd 15 1.35 1.5 1.65 v input voltage range (5v withstand voltage pin) v in 5 0 5.5v input voltage range (non-5v withstand voltage pin) v in 0 3.9v
LC74950BG no.a1647-3/37 dc characteristics at ta = -30 to +70 c, dv dd 33 = 3.3v 0.3v (other than low-voltage support models), dv dd 15= 1.5 10% ratings parameter symbol conditions min typ max unit cmos level inputs (5v withstand voltage pin) 0.8dv dd 33 5.5 v cmos level inputs (2.4v to 3.6v or non-5v withstand voltage pin) 0.8dv dd 33 dv dd 33 v cmos level schmitt inputs (5v withstand voltage pin) 2.0 5.5 v input high-level voltage v ih cmos level schmitt inputs (2.4v to 3.6v or non-5v withstand voltage pin) 0.8dv dd 33 dv dd 33 v cmos level inputs 0 0.2v dd 33 v input low-level voltage v il cmos level schmitt inputs 0 0.2v dd 33 v v i =dv dd 10 a input high-level current i ih v i =dv dd , with pull-down resistance 100 a input low-level current i il v i =v ss -10 a output high-level voltage v oh cmos (pin g/i: i oh =-4ma, pin f: when set to -6ma) dv dd -0.6 v output low-level voltage v ol cmos 0.4 v output leak current i oz at output of high-impedance -10 10 a 3.0v to 3.6v 58 k pull-down resistor r dn 2.4v to 3.6v 70 k dynamic supply current (dv dd 33) outputs open, tck=27mhz natural image, ta=25 c 13 ma dynamic supply current (dv dd 15) tck=27mhz: natural image, ta=25 c 7 ma dynamic supply current (av dd 33) tck=27mhz: natural image, ta=25 c 52 ma dynamic supply current (av dd 15) i ddop tck=27mhz: natural image, ta=25 c 0.1 ma static supply current: *1 i ddst outputs open, v i =v ss , ta=25 c 10 a * 1: there is an input terminal which builds in pull down resist ance. please note that there is no guarantee about static consumption current depending on circuit composition. a/d convertor characteristics at ta = 25 c, dv ss = 0v, av ss = 0v parameter symbol/pin min typ max unit adc resolution 9bit clock frequency fclk 5 40mhz snr 48 db dnl 0.5 lsb inl 1.0 lsb external capacitance analog input coupling capacitance analog video pin 0.1 f top level reference fixed capacitance vrtx pin 0.01 f bottom level reference capacitance vrbx pin 0.01 f analog input frequency fain 10 mhz analog input amplitude 1.0 v adc stabilization time (time required to restore from standby mode) 500 ms pll lock time 3 ms
LC74950BG no.a1647-4/37 package dimensions: fbga96 unit: mm (typ) 3387 pin assignment sanyo : isb96(6.0x6.0) 12345678910 a b c d e f g h j k 6.0 6.0 0.75 0.5 0.75 0.5 0.1 1.05 max 0.29 side view side view top view bottom view LC74950BG top view b c d e f g h j k 1 2 3 4 5 6 7 8 9 10 a
LC74950BG no.a1647-5/37 block diagram pin functions in/output format pin no. pin symbol i/o format connecting destination remarks a1 adc2av ss 33 p gnd analog it must be treated in the same way as an nc pin. a2 cbout0 i/o i 3.3v cmos digital video signal output cb or b (lsb) a3 cbout2 i/o i 3.3v cmos digital video signal output cb or b a4 cbout4 i/o i 3.3v cmos digital video signal output cb or b a5 cbout6 i/o i 3.3v cmos digital video signal output cb or b a6 pdwn i b 3.3v cmos digital power down ?l? power down a7 av ss 33_pll p gnd analog a8 chrgpmp o a analog filter input a9 av dd 33_pll p 3.3v analog pll power supply a10 dv dd 15 p 1.5v digital b1 vrt2 i a analog top level reference voltage connection pin for adc2 b2 adc2av ss 33 p gnd analog b3 cbout1 i/o i 3.3v cmos digital video signal output cb or b b4 cbout3 i/o i 3.3v cmos digital video signal output cb or b b5 cbout5 i/o i 3.3v cmos digital video signal output cb or b b6 cbout7 i/o i 3.3v cmos digital video signal output cb or g (msb) b7 dv ss p gnd digital b8 av ss 33_pll p gnd analog b9 dv dd 15 p 1.5v digital it must be treated in the same way as an nc pin. b10 hsin i b 3.3v cmos digital horizontal synchronizing signal c1 crin1 i a to 1.0vp-p analog analog cr or r input (adc2) c2 vrb2 i a analog bottom level reference voltage connection pin for adc2 c3 adc2av dd 33a p 3.3v analog c4 dv ss p gnd digital c5 dv ss p gnd digital c6 dv ss p gnd digital c7 dv dd 15 p 1.5v digital c8 dv dd 15 p 1.5v digital c9 vsin i b 3.3v cmos digital vertical synchronizing signal c10 reset i b 3.3v cmos digi tal system reset ?l? reset continued on next page. LC74950BG g / y b / cb r / cr clamp clamp clamp adc adc adc clamp clamp clamp hs / vs pll clk sw i 2 c sda scl g / y b / cb r / cr hs / vs de clk 8 reset sw gain gain gain r / cr sw g / y sw b / cb sw sw power down 9
LC74950BG no.a1647-6/37 continued from preceding page. in/output format pin no. pin symbol i/o format connecting destination remarks d1 vrt1 i a top level reference voltage connection pin for adc1 d2 crin0 i a to 1.0vp-p analog analog cr or r input (adc2) d3 adc1av ss 33 p gnd analog d4 dv ss p gnd digital d5 dv ss p gnd digital d6 dv ss p gnd digital d7 dv dd 15 p 1.5v digital d8 dv dd 15 p 1.5v digital d9 clkout2 o f 3.3v cmos digital clkout1 2 output or pll output d10 clkout1 o f 3.3v cmos digita l datasynchronization clock output e1 cbin1 i a to 1.0vp-p analog analog cb or b input (adc1) e2 vrb1 i a bottom level reference voltage connection pin for adc1 e3 adc1av dd 33a p 3.3v analog e4 dv ss p gnd digital e7 dv dd 15 p 1.5v digital e8 i 2 csel i c 3.3v cmos i 2 c slave addresses l=0 98, h=0 9a e9 scl i d digital e10 coast i b 3.3v cmos digital connected to gnd f1 vrt0 i a analog top level reference voltage connection pin for adc0 f2 cbin0 i a to 1.0vp-p analog analog cb or b input (adc1) f3 adc0av ss 33 p gnd analog f4 dv ss p gnd digital f7 dv dd 15 p 1.5v digital f8 test i h 3.3v cmos digital test pin (normally fixed low) f9 sda i/o g digital f10 clkin i d 3.3v cmos digital system clock (must be connected to gnd when not to be used) g1 ygin1 i a to 1.0vp-p analog analog y or g input (adc0) g2 vrb0 i a analog bottom level reference voltage connection pin for adc0 g3 adc0av dd 33 p 3.3v analog g4 scanen i h 3.3v cmos di gital test pin (normally, lo) g5 dv dd 33 p 3.3v digital g6 dv dd 33 p 3.3v digital g7 dv dd 33 p 3.3v digital g8 dv dd 33 p 3.3v digital g9 hsout i/o i 3.3v cmos digital horizontal synchronizing signal g10 vsout i/o i 3.3v cmos digital vertical synchronizing signal h1 atb o a analog output for testing the adc. it must be held open when not to be used. h2 ygin0 i a to 1.0vp-p analog analog y or g input (adc0) h3 av dd 15_osc p 1.5v analog power supply for the rc oscillator h4 scanmod i h 3.3v cmos digital test pin (normally, lo) h5 dv dd 33 p 3.3v digital h6 dv dd 33 p 3.3v digital h7 dv dd 33 p 3.3v digital h8 dv dd 33 p 3.3v digital h9 crout7 i/o i 3.3v cmos digital video signal output cr or r (msb) h10 deout i/o i 3.3v cmos digital data enabl e. it must be held open when not to be used. continued on next page.
LC74950BG no.a1647-7/37 continued from preceding page. in/output format pin no. pin symbol i/o format connecting destination remarks j1 svo o a to 1.0vp-p analog test pin. it must be held open when not to be used. j2 av ss _osc p gnd analog j3 ygout1 i/o i 3.3v cmos digital video signal output y or g j4 ygout7 i/o i 3.3v cmos digital video signal output y or g (msb) j5 ygout4 i/o i 3.3v cmos digital video signal output y or g j6 crout0 i/o i 3.3v cmos video signal output cr or r (lsb) j7 crout3 i/o i 3.3v cmos digital video signal output cr or r j8 crout5 i/o i 3.3v cmos digital video signal output cr or r j9 dv dd 33 p 3.3v digital j10 crout6 i/o i 3.3v cmos digital video signal output cr or r k1 av ss _osc p gnd analog it must be treated in the same way as an nc pin. k2 ygout0 i/o i 3.3v cmos digital video signal output y or g (lsb) k3 ygout2 i/o i 3.3v cmos digital video signal output y or g k4 ygout3 i/o i 3.3v cmos digital video signal output y or g k5 ygout5 i/o i 3.3v cmos digital video signal output y or g k6 ygout6 i/o i 3.3v cmos digital video signal output y or g k7 crout1 i/o i 3.3v cmos video signal output cr or r k8 crout2 i/o i 3.3v cmos digital video signal output cr or r k9 crout4 i/o i 3.3v cmos digital video signal output cr or r k10 dv dd 33 p 3.3v digital it must be treated in the same way as an nc pin.
LC74950BG no.a1647-8/37 pin type in/output form function equival ent circuit application terminal a analog input/output chrgpmp, crin0, crin1, vrt2, vrb2, cbin0, cbin1, vrt1, vrb1, ygin0, ygin1, vrt0, vrb0, svo, atb b 5v withstand schmitt trigger cmos input * hsin, pdwn, vsin, coast, reset c 5v withstand cmos input with built-in pull-down resistor * i 2 csel d 5v withstand cmos input * clkin, scl f 12ma switching 3-state drive cmos output ckout1, ckout2 g 8ma 3-state drive cmos input/output * (5v withstand) sda h cmos input with built-in pull-down resistor test, scanen, scanmod i 8ma 3-state drive cmos input/output hsout, vsout, deout, crout0, crout1, crout2, crout3, crout4, crout5, crout6, crout7, cbout4, cbout5, cbout6, cbout7, cbout0, cbout1, cbout2, cbout3, ygout0, ygout1, ygout2, ygout3, ygout4, ygout5, ygout6, ygout7 * : 5v tolerant
LC74950BG no.a1647-9/37 pin connection 1) adc and its peripherals 2) pll and its pereipherals 3) output pin (recommended) 4) power supplies the analog a** and digital d** power supplies must be su pplied separately without fa il. in addition, the power supply for the pll circuit must also be provided separately as it will affect the jitter charac teristics of the pll circuit. for adc power supply, it is desirable to provide separate power for eachof the adc channel. av dd 33_pll : must be separated by l components, etc. adc2av dd 33a : separating by l comp onents, etc. recommended adc1av dd 33a : separating by l comp onents, etc. recommended adc0av dd 33a : separating by l comp onents, etc. recommended 5) unused pin treatment ygin0, 1/cbin0, 1/crin0, 1: open pdwn: pull up chrgpmp: open (when pll is not in use) ***out* (e.g., ygout0): open hsin/vsin: must always be configured for input. reset: must always be configured for input. coast: must be connected to dv ss . test, scanen, scanmod: dv ss clkin: dv ss hsout, vsout, deout: open svo, atb: open * the specified voltage of power must be applied to each of the power supply pin even if it is not to be used (pll is not to be used, for example). 10 0.0039
LC74950BG no.a1647-10/37 i/o data timing (1) input data timing pin name parameter symbol min typ max unit clock cycle t ck 25 ns clkin duty 50 % input data setup time (dv dd 33=3.0 to 3.6v) t su 3.0 ns input data setup time (dv dd 33=2.4 to 3.6v) t su 3.0 ns input data hold time (dv dd 33=3.0 to 3.6v) t hd 3.0 ns hsin, vsin input data hold time (dv dd 33=2.4 to 3.6v) t hd 3.0 ns * : the recommended duty cycle of input clock is 50% (2) output data timing pin name parameter symbol min typ max unit clock cycle t ck 25 ns clkout1 duty 50 % output data delay time (3.0 to 3.6v) t ac 0 2.0ns output data delay time (2.4 to 3.6v) t ac 0 3.0ns output data hold time (3.0 to 3.6v) t hd 3.0 ns ygout*, cbout*, crout*, hsout ,vsout, deout output data hold time (2.4 to 3.6v) t hd 3.0 ns * when clkout1 is set to the forward rotation output. v dd 33/2 t hi t lo t ck t su t hd clkin v dd 33/2 input data t lo t ck t ac clkout1 output data v dd 33/2 v dd 33/2 t hi t hd
LC74950BG no.a1647-11/37 timing chart note: for the initial setting of the registers details of the functions 1. selection of input pins registers related to the selection of input pins name functions sub address bit width ainsel video input select control analog video input select 0: ygin0/cbin0/crin0 1: ygin1/cbin1/crin1 0x22 1 ? video input selector function the video input signal used for actual processing can be selected out of the two systems of video input. ainsel=0: ygin0/cbin0/crin0 ainsel=1: ygin1/cbin1/crin1 2. input format registers related to the selection of the input format name functions sub address bit width selycrgb this register switches be tween the ycbcr input and rgb input. 0: ycbcr, 1: rgb 0x14 1 syncon for ycbcr input, this register, by cutting off the digitally clamped sync component of the y video signal, sets the applicable gain adjustment function to on or off. this must be set to 0 for the rgb input (selycrgb=1). 0: on, 1: off 0x1b 1 all the inputs listed below can be connected to the analog ports. it is also possible to switch between the inputs of two systems and use the one selected. ycbcr/ypbpr input (480i/576i, 480p/576p): component input rgb: rgb input 3. operating modes register related to the selection of operating mode name functions sub address bit width clksel operating mode selection 000: external clock mode (pll not used) 001: external clock mode (pll used) 010: h lock pll mode 011: panel pll mode <1> 100: panel pll mode <2> 0x00 3 n clkin output data analog input n+1 n+2 n-50 n-49 n n+1
LC74950BG no.a1647-12/37 1) external clock mode (pll not used: clkout1=clkin/2, clkout2=clkin) example: component input (ntsc) (down sample) 2) external clock mode (pll used: clkout1=clkin, clkout2=clkin*2) example: component input (ntsc) (2 clock generation) g/y b/cb r/cr LC74950BG 8 8 8 r out b out g out adc analog self- clamping digital clamp gain offset hs out vs out de out clkout1 vs in pdown i 2 c clkout2 timing generator 27mhz ckgen reset 13.5mhz hs in clk in (27mhz) pll s e l s e l 1/2 1/2 s e l g/y b/cb r/cr 8 8 8 r out b out g out digital clamp gain offset hs out vs out de out clkout1 vs in pdown clkout2 27mhz ckgen reset 13.5mhz hs in clk in (13.5mhz) pll s e l s e l 1/2 1/2 s e l LC74950BG adc analog self- clamping i 2 c timing generator
LC74950BG no.a1647-13/37 3) h-lock pll mode (pll used: clkout1=hs/divide, clkout2=clkout1*2) example: component input (ntsc) (2 clock generation) 4) adc/pll independent mode <1> (external clock input, pll configured independently: clkout1=clkin/2, clkout2=clkin/in-divide*out- divide) example: component (adc down sample), pll: generation of separate system clock i 2 c g/y b/cb r/cr 8 8 8 r out b out g out digital clamp gain offset hs out vs out de out clkout1 vs in pdown clkout2 27mhz ckgen reset 13.5mhz hs in clk in pll s e l s e l 1/2 1/2 s e l LC74950BG adc analog self- clamping timing generator g/y b/cb r/cr 8 8 8 r out b out g out digital clamp gain offset hs out vs out de out clkout1 vs in pdown clkout2 33mhz ckgen reset hs in clk in (27mhz) pll s e l s e l 1/2 1/2 s e l 13.5mhz LC74950BG adc analog self- clamping i 2 c timing generator
LC74950BG no.a1647-14/37 5) adc/pll independent mode <2> (external clock input, pll configured separately: clkout1=clkin, clkout2=clkin/in-divide*out-divide) example: component (adc down sample), pll: generation of separate system clock 4. clock system 1) clock system diagram *1 explanation of signals fout: a clock generated in the pll circuit and synchronized with the reference signal (fin). the frequency of fin and pll divider value (hpldiv, 28h-29h, bits 15-0) determine the frequency of fout. foutx2: a clock generated in the pll circuit and synchronized with the reference signal (fin). the frequency of foutx2 is two times of the frequency of fout. clkout: a clock generated in the adc. to output the clock it is necessary to adjust the phase of the sampling clock (clkadc) in order that the rising edge of the clock does not occur near the change point of the adc sampled data. clkadcinv 00h, bit2-0 fout *1 foutx2 *1 clksel 00h, bit3 1/2 divider pll clksel 00h, bit2-0 3 / 3 / c clkout2inv 00h, bit7 clkout1inv 00h, bit6 clkout *1 clkoutinv 01h, bit7 clkout2 *2 clkout1 *2 clkin powerin clkindiv clksel 40h, bit5-0 00h, bit4 clkininv 00h, bit2-0 03h, bit3 hsinv / 6 1/1 to 1/64 divider hsin fin logic adc clkadc *2 i 2 c g/y b/cb r/cr 8 8 8 r out b out g out digital clamp gain offset hs out vs out de out clkout1 vs in pdown clkout2 33mhz ckgen reset 13.5mhz hs in clk in (13.5mhz) pll s e l s e l 1/2 1/2 s e l lc74950adc adc analog self- clamping timing generator
LC74950BG no.a1647-15/37 registers related to the control of clock name functions sub address bit width clkininv this register contro ls the inversion of clkin when the clkin input is used as a reference clock to pll. 0: uses clkin in its original form 1: uses clkin in its inverted form 0x00 2 hsinv this register controls the inversion of hsin input. the hsin must be used in its inverted form when the polarity of hsin input is negative. 0: original form (when hsin is positive) 1: inverted form (when hsin is negative) 0x02 1 clkindiv this register sets the frequency divi sion ratio of clkin to an arbitrary value (1/1 to1/64) when the clkin is used as a reference clock to pll. 1/(clkindiv[5:0]+1) division 0x40 6 clksel this register selects the operating mode. 000: (external clock mode (pll not used) 001: (external clock mode (pll used) 010: h-lock pll mode 011: panel pll mode <1> 100: panel pll mode <2> 0x00 3 clkadcinv this register controls the inve rsion of the adc sampling clock (clkadc). 0: uses clkadc in its original form 1: uses clkadc in its inverted form 0x00 1 clkoutinv this register controls the inve rsion of the adc-generated clock. (clkout). 0: uses clkout in its original form 1: uses clkout in its inverted form 0x01 1 clkout1inv this register c ontrols the inversion of clkout (video clock output). 0: original form 1: inverted form 0x00 1 clkout2inv this register c ontrols the inversion of cl kout2 (panel clock output). 0: original form 1: inverted form 0x00 1 *2 clock control register (clksel, 00h, bits 2-0) specifications clksel (bit2-0) clkadc*3 (adc sampling clock) fin (pll reference) clkout2 (clock output) remarks 000 clkin/2 (13.5mhz) l fixed (pll not used) clki n(27mhz) external clock mode (pll not used) 001 fout (pll output) clkin *4 foutx2 (pll output x2) external clock mode (pll used) 010 fout (pll output) hsin *5 foutx2 (pll output x2) h-lock pll mode 011 clkin/2 clkin *4 fout (pll output) panel pll mode <1> 100 clkin clkin *4 fout (pll output) panel pll mode <2> *3: register clkadcinv (00h, bit 3) allows for clock inversion. *4: register clkindiv (40h, bits 5-0) allows for division of clock frequency (1/1 to 1/64). *5: register hsinv (03h, bit 3) allows for hsin inversion.
LC74950BG no.a1647-16/37 2) pll circuit this circuit can be used as the h lock or frequency-multip lied clock. it is also possible to use the pll circuit and analog-digital converter (adc) independently. h lock pll circuit: this makes it possible to generate a clock that is synchronized with the external h sync signal. frequency-multiplier pll circuit: this makes it possible to generate clocks that are synchronized with an external clock. registers related to the setting of pll circuit name functions sub address bit width clkininv this register contro ls the inversion of clkin when the clkin input is used as a reference clock to pll. 0: uses clkin in its original form 1: uses clkin in its inverted form 0x00 2 hsinv this register controls the inversion of hsin input. the hsin must be used in its inverted form when the polarity of hsin input is negative. 0: original form (when hsin is positive) 1: inverted form (when hsin is negative) 0x02 1 clkindiv this register sets the frequency divi sion ratio of clkin to an arbitrary value (1/1 to 1/64) when the clkin is used as a reference clock to pll. 1/(clkindiv[5:0] 1) division 0x40 6 clksel this register selects the pll reference input. 000: l fixed (pll not used) 001: external clock input (clkin) 010: external hsync input (hsin) 011: external clock input (clkin) 100: external clock input (clkin) 0x00 3 hpldiv15-12 this register sets the out put divider (m-1, ntsc, 480i=3). 0x28 4 hpldiv11-0 this register sets the feedback divider (n-2, ntsc, 480i=856). h-lock pll output frequency (1x)=hsync frequency n h-lock pll output frequency (2x)=hsync frequency n 2 * after changing the setting, an interval of 3.0ms is required for the h-lock pll to get stabilized. 0x28 0x29 12 continued on next page. fin pll vco output divider (m=1 to 16) fout 2 feedback divider (n=2 to 4097) 1/2 fout clkin powerin clkindiv clksel 40h, bit5-0 00h, bit4 clkininv 00h, bit2-0 03h, bit3 hsinv / 6 1/1 to 1/64 divider hsin foutx2 frequency=(fin frequency) m 2 n fout frequency=(fin frequency) m n
LC74950BG no.a1647-17/37 continued from preceding page. name functions sub address bit width pllgain this register switches the setting of fmin, fmax, and gain of the h-lock pll vco. 000: fmin=60mhz, fmax =240mhz, gain=120mhz/v standard setting 001: fmin=standard, fmax=standar d-20%, gain=standard-22.5% 010: fmin=standard-20%, fmax=standard, gain=standard+2.5% 011: fmin=standard-20%, fmax=standard-20%, gain=standard-20.0% 100: fmin=standard+20%, fmax=standard+10%, gain=standard+8.75% 101: fmin=standard+20%, fmax=standard-10%, gain=standard-13.75% 110: fmin=standard, fmax=standar d+10%, gain=standard+11.25% 111: fmin=standard, fmax=standar d-10%, gain=standard-11.25% * after changing the setting, an interval of 3.0ms is required for the h-lock pll to get stabilized. 0x27 3 pllctl2 h-lock pll power down mode 0: normal operation 1: h-lock pll power off 0x27 1 pllctl1 h-lock pll normal mode fout disable 0: normal operation 1: h-lock pll output= l fixed 0x27 1 cpis_coast cpis_org these registers set the pll charge pump constant current (make sure that cpis_coast=cpis_org) 0000: 40 a 0001: 60 a 0010: 120 a 0011: 180 a 0100: 200 a 0110: 280 a 0101: 300 a 1000: 360 a 0111: 420 a 1010: 440 a standard setting 1100: 520 a 1001: 540 a 1110: 600 a 1011: 660 a 1101: 780 a 1111: 900 a * after changing the setting, an interval of 3.0ms is required for the h-lock pll to get stabilized. 0x2a 4 pll setting example (when using as h-lock pll) ref [khz] clksel [2:0] plldiv 15-12 plldiv 11-0 fvco* [mhz] foutx2 [mhz] fout [mhz] cpis [3:0] pllgain [2:0] ntsc 15.734 2h 3h 6b2h 216 (54) 27 ch 0h ntsc 15.734 2h 7h 358h 216 27 13.5 ch 0h pal 15.630 2h 3h 6beh 216 (54) 27 ch 0h pal 15.630 2h 7h 35eh 216 27 13.5 ch 0h pal-n 15.630 2h 7h 35eh 216 27 13.5 ch 0h pal-m 15.734 2h 7h 358h 216 27 13.5 ch 0h qvga 15.70 2h fh 1a6h 213 13.3 6.68 ch 0h vga 31.5 2h 3h 31eh 201 (50.4) 25.2 ch 0h wvga 31.0 2h 3h 41eh 262 (65.4) 32.7 dh 0h * 20mhz < fvco < 340mhz
LC74950BG no.a1647-18/37 5. timing control 1) deout (enable output) setting registers related to the setting of enable name functions sub address bit width hblks this register specifies the 1h start position of deout in dot units. set value smaller than hblke. 0x04 0x05 12 hblke this register specifies the 1h end position of deout in dot units. set the value that is larger than hblks and does not overlap the next hsync. 0x04 0x06 12 vblks this register specifies the 1v start position of deout in line units. set the value smaller than vblke. 0x07 0x08 11 vblke this register specifies the 1v end position of deout in line units. set the value that is larger than vblks and does not overlap the next vsync. 0x07 0x09 11 ? setting of horizontal enable *1: deout is forcibly disabled at the leading edge of the next hsout even if hblke[11:0] is set with a value larger than the total pixel count of 1h. ? setting of vertical enable *2: deout is forced disabled at the leading edge of the next vsout even if vblke[10:0] is set with a value larger than the total line count of 1v. r0 r1 r2 ... r1439 g0 g1 g2 ... g1439 b0 b1 b2 ... b1439 hblks [11:0] hblke [11:0] *1 clkout1 hsout crout7-0 ygout7-0 cbout7-0 deout vblks [10:0] vblke [10:0] *2 hsout vsout crout7-0 ygout7-0 cbout7-0 deout active line active line active line
LC74950BG no.a1647-19/37 2) sync width adjustment (h-lock pll mode only) of horizontal sync output (hsout) registers related to sync width adjustment of hsout name functions sub address bit width hspllsel this register selects the horizontal sync signal (shout) in the h-lock pll mode. 0: hsin 1: this is the signal that is fed back to the phase detector after dividing the vco output of the pll. *: sync width adjustment for hsout must be turned on when hspllsel is set to 1. 0x01 1 corren this register turns on and off the sync width adjustment for hsout. 0: off, 1: on 0x27 1 corrhss sync width adjustment register fo r hsout (to be described below) 0x2b 0x2c 12 corrhse sync width adjustment register fo r hsout (to be described below) 0x2b 0x2d 12 when "1" is set for hspllsel in the h lock pll mode, the horizontal sync output signal is not hsin but the signal that is fed back to the phase detector after dividing the vco output of the pll. the duty ratio of this signal is 50%, which means when it is to be used as the horizontal sync signal, the sync width must be determined. furthermore, if "0" is set for hspllsel, the horizontal sync input (hsin) signal can be output in its original form even in the h lock pll mode. * 1: clock is expressed in units of clkout1. * 2: a value equivalent to about three-fourths of one hsout period (640 or so with the ntsc system) must be set as the corrhse[11:0] value. (corrhss [11:0] + 3) clock *1 corrhse [11:0] *2 hsout (hsoutinv=0) feedback signal to the phase detector
LC74950BG no.a1647-20/37 3) offset adjustment of video output registers related to video output offset adjustment name functions sub address bit width asyg this register adjusts the offset for the y/g video signal. it is used when the timing between the video signal and sync signals is off. the y/g video signal can be shifted by an amount equivalent to (asyg + 1) locks. 0x01 3 ascrr this register adjusts the offset for the cr/r video signal. it is used when the timing between the video signal and sync signals is off. the cr/r video signal can be shifted by an amount equivalent to (ascrr + 1) clocks. 0x02 3 ascbb this register adjusts the offset for th e cb/b video signal. it is used when the timing between the video signal and sync signals is off. the cb/b video signal can be shifted by an amount equivalent to (asvbbyg + 1) clocks. 0x02 3 asvs this register adjusts the offset for the vsout video signal. it is used when the timing between the video signal and sync signals is off. the vertical sync signal can be shifted by an amount equivalent to (asvs + 1) clocks. 0x03 3 ashs this register adjusts the offset for th e hsout. it is used when the timing between the video signal and sync signals is off. the horizontal sync signal can be shifted by an amount equivalent to (ashs + 1) clocks. 0x03 3 ? offset adjustment method if the following fluctuations are present between the video outputs when asyg[2:0] = 000b, ascrr[2:0] = 000b and ascbb[2:0] = 000b: then, by setting asyg[2:0] = 010b, ascrr[2:0] = 000b and ascbb[2:0] = 011b, the video outputs can be aligned as shown below. the maximum shift width of the video signals is 8 clocks. if the asvs[2:0] and ashs[2:0] registers are used in line with the video signal shift, the sync signa ls (vsout and hsout) can also be shifted in line with the video signals. (deout is also shifted following hsout.) r0 r1 r2 ... r1439 g0 g1 g2 ... g1439 b0 b1 b2 ... b1439 clkout1 crout7-0 ygout7-0 cbout7-0 r0 r1 r2 ... r1439 g0 g1 g2 ... g1439 b0 b1 b2 ... b1439 clkout1 crout7-0 ygout7-0 cbout7-0
LC74950BG no.a1647-21/37 6. adc 1) analog clamp registers related to analog clamp control name functions sub address bit width stbb this register controls the band gap vref circuit. 0: band gap vref circuit enters standby mode. 1: band gap vref circuit enters normal operating mode. * this must be set in line with the operation mode of adc. 0x21 1 stbb_y stbb_b stbb_r these registers control the afe standby mode (y: stbb_y, b: stbb_b, r: stbb_r) 0: afe standby mode 1: afe normal operating mode * this must be set in line with the operation mode of adc. 0x21 0x23 0x25 1 selfclpstbb_y selfclpstbb_b selfclpstbb_r these registers control self-clamp. (y: selfclpstbb_y, b: selfcl pstbb_b, r: selfclpstbb_r) 0: self-clamp function is off 1: self-clamp function is on *1: this is disabled when stbb_x=0 (self-clamp function is off). *2: the clamp level is set to mainclplvcnt_x[1:0]. 0x21 0x23 0x25 1 mainclplvcnt_y mainclplvcnt_b mainclplvcnt_r these registers control the clamp level. (y: mainclplvcnt_y, b: maincl plvcnt_b, r: mainclplvcnt_r) 00: 0.35v (sink tip clamp) 01: 0.50v (pedestal clamp) 10: 0.85v (center clamp) 11: inhibited. *: this is enabled when the self-clamp is on. (stbb_x=1, selfclpstbb_x=1) 0x22 0x24 0x26 2 hpfclpon_y hpfclpon_b hpfclpon_r these registers contro l hpf center clamp. (y: hpfclpon_y, b: hpfc lpon_b, r: hpfclpon_r) 0: hpf center clamp is off 1: hpf center clamp is on *: this must be set off unless the center clamp is selected. (mainclplvcnt_x[1:0]=10). 0x22 0x24 0x26 1 clplpfon_y clplpfon_b clplpfon_r these registers control clamp lpf. (y: clplpfon_y, b: clpl pfon_b, r: clplpfon_r) 0: lpf function is off 1: lpf function is on *: this is appropriate for rejecting high-frequency noises in a weak electric field (cut-off frequency is 1mhz). this must be set off when the video signals equi valent to hd specifications is input. 0x22 0x24 0x26 1
LC74950BG no.a1647-22/37 ? analog clamp function this function performs sync tip clamping and pedestal clamping to the video input selected by ainsel. when the analog clamp function is not used, it can be placed in the standby stat us using the self clpstbb_x setting. stbb_x selfclpstbb_x state clamping voltage 0 * analog clamp function off - 1 0 analog clamp function off - 1 1 analog clamp function on subjec ted to the clamp level control ? analog clamp level control when the analog clamp function is on, sync tip clamp, pe destal clamp and center clamp can be selected using the settings below. mainclplvcnt[1:0] clamp level state/use 00 0.35v sync tip clamp 01 0.50v pedestal clamp 10 0.85v center clamp 11 - inhibited the clamp levels applied to the ycbcr and rgb inputs are given below. afe ch ycbcr rgb y sync chip clamp pedestal clamp b center clamp pedestal clamp r center clamp pedestal clamp
LC74950BG no.a1647-23/37 ? sync tip clamp specifications ? center clamp specifications the figures represent the set va lues set under ideal conditions. 511 1 256 1.0vp-p 0.35v a nalog input digital output 1.35v clamp settings self-clamp setting selfclpstbb h: self-clamp on main clamp level setting mainclplvcnt [1:0] 00: main clamp level set to 0.35v hpf center clamp setting hpfclpon l: hpf clamp off s/h gain setting gain l: 1 gain 0.85v (adc-input reference) 0.65v 1.55v 0.15v a dc output code s/h gain setting gain=l 1 gain 73 439 1.4vp-p range *the figures represent the set va lues set under ideal conditions. 511 1 256 0.7vp-p 0.325v a nalog input digital output 1.375v 0.85v (adc-input reference) 0.50v 1.55v 0.15v digital output 64 448 1.4vp-p range 1.20v s/h gain setting gain=h 1.5 gain clamp settings main clamp level setting mainclplvcnt [1:0] 10: main clamp level set to 0.85v self-clamp setting selfclpstbb l: self-clamp off hpf center clamp setting hpfclpon h: hpf clamp on s/h gain setting gain h: 1.5 gain
LC74950BG no.a1647-24/37 ? pedestal clamp specifications ? clamp lpf function a primary lpf with a 1mhz cutoff frequency has been inserted in the stage before the self-clamp circuit as a measure to deal with the high-frequency noise that is present in weak electrical fields. the clamp lpf function is for minimizing shifts in the clamp levels of the self-clamp and sub-clamp when high-frequ ency noise components are present in the video signals. the lpf can be set to on or off using the clplpfon setting. it must be set to on when sd standard signals are input, and set to off when hd standard signals are input. the cutoff frequency of the lpf is 1mhz. care must therefore be taken when the lpf is set to on since the clamp level will drop when hd standard signals are input because it is not possible to track frequencies corresponding to the sync width. input video signal (sd) high-frequency noise with frequencies of 1mhz and above 0v 0.35v sink tip clamp when lpf is off. clamping is performed at the lower limit level of the noise components. due to the effect of the noise, the clamp level shifts. clamping is performed at the level at which the noise components are removed. it is clamped at its original position. sink tip clamp when lpf is on. * the figures represent the set values set under ideal conditions. 511 1 256 0.7vp-p 0.325v a nalog input digital output 1.20v 0.85v (adc-input reference) 0.50v 1.55v 0.15v digital output 64 448 1.4vp-p range 1.375v s/h gain setting gain=h 1.5 gain clamp settings self-clamp setting selfclpstbb h: self-clamp on main clamp level setting mainclplvcnt [1:0] 01: main clamp level set to 0.50v hpf center clamp setting hpfclpon l: hpf clamp off s/h gain setting gain h: 1.5 gain
LC74950BG no.a1647-25/37 2) adc registers related to adc control name functions sub address bit width stbl_y stbl_b stbl_r these registers control the adc standby m ode (y: stbl_y, b: stbl_b, r: stbl_r). 0000: adc standby mode 1111: adc normal operating mode *1: any other settings than above inhibited. *2: this must be set in line wi th the operating mode of adc. 0x21 0x23 0x25 4 icnt_y icnt_b icnt_r these registers control the internal bias current of adc (y: icnt_y, b: icnt_b, r: icnt_r). bias current generating resistor values: 000: 600 (recommended) 001: 540 010: 480 011: 420 100: 360 101: 300 110: 240 111: 180 0x39 0x3a 0x3b 3 7. digital clamp 1) digital clamp pulses registers related to digital clamp pulse control name functions sub address bit width osel this register sets the digital clamp pulse output to on or off. it is used to adjust the positi on of the digital clamp pulses. 000: normal operation 101: the y digital clamp pulse is output from the ygout7 pin and the c digital clamp pulse is output from the cbout7 pin. 0x2e 3 dclpyon dclpcon these registers set the digital clamp pulse to on and off (y: dclpyon, c: dclpcon). 0: off, 1: on 0x0a 0x0f 1 dcpyset dcpcset these registers set the digital clamp pu lse positions (y: dcpyset, c: dcpcset). they are set in 4-clock increments using t he trailing edge of hsync as a reference. setting range: -32 (00h) to +31 (3fh), default value: +/-0 (20h) 0x0a 0x0f 6 dclpyw dclpcw these set the digital clamp pulse width. it can be set in 1 clock increments. 0 specifies a pulse width of 0. (y: dclpyw, c: dclpcw) 0x0b 0x10 6 dclpyv dclpcv these registers set the disable function of t he digital clamp pulses during the vertical blanking period to on or off. (y: dclpyv, c: dclpcv) 0: off, 1: on 0x0b 0x10 1 dcpyvms dcpcvms these specify the start line at which the digital clamp pulses are enabled within 1v. as a basic rule, the same values as the v-enable start line (vblks[10:0]) are set. 0x0c-0x0d 0x11-0x12 11 dcpyvme dcpcvme these specify the end line at which the digital clamp pulses are enabled within 1v. as a basic rule, the same values as the v-enable end line (vblks[10:0]) are set. 0x0c-0x0e 0x11-0x13 11 digital clamp pulse settings (how to output the clamp pulses) osel[2:0] *1 ygout7 cbout7 101 digital clamp pulse (y) digital clamp pulse (c) *1: the "000" setting must be used during normal operation.
LC74950BG no.a1647-26/37 ? digital clamp pulse settings (how to establish settings in the horizontal direction) *2: the digital clamp pulse positions must be set so that they come within the horizontal blanking period (deout = l). *3: the digital clamp pulse (c) setting method is the same as that described above. however, dcpcset[5:0] (0fh, bit5-0) must be used for the pulse position setting, and dclpcw[5:0] (10h, bit5-0) must be used for the pulse width setting. ? digital clamp pulse settings (how to establish settings in the vertical direction) *4: by using the digital clamp pulse disable function (y: dclpyv = 1, c: dclpcv = 1), the digital clamp pulse in the vertical blanking period can be set to off. the same values as the vertical enable settings (vblks[10:0], vblke[10:0]) must be used for the mask peri od settings (dcpyvms[1 0:0], dcpyvme[10:0]). *5: the digital clamp pulse (c) setting method is the same as that described above. however, dcpcvms[10:0] and dcpvme[10:0] must be used for the mask period settings. dcpyvme [10:0] hsout vsout deout ygout7 dcpyvms [10:0] dclpyw [5:0] dcpyset [5:0] 4+1 clkout1 hsout deout ygout7<1> dcpyset [5:0] >when 20h ygout7<2> when dcpyset [5:0] when < 20h dcpyset [5:0] 4-1 dclpyw [5:0] dclpyw [5:0] 1clock ygout7<3> dcpyset [5:0] when = 20h
LC74950BG no.a1647-27/37 2) digital clamp registers related to digital clamp control name functions sub address bit width selycrgb this register switches be tween the ycbcr input and rgb input. 0: ycbcr, 1: rgb 0x14 1 stdlevy yg digital clamp levels (selycrgb=0: y, selycrgb=1: g) the 9-bit (0-511) yg video signals are clamped by the values determined assuming the pedestal levels (y: stdlevy[5:0] + 118, g: stdlevy[5:0]). setting range: y (118-181), g (0-63) 0x14 6 stdlevcb cbb digital clamp levels (selycrgb=0: cb, selycrgb=1: b) the 9-bit (0-511) cbb video signals are clamped by th e value determined assuming the center level (stdlevcb[5:0] + 225) for cb and the pedestal level (stdlevcb[5:0]) for b. setting range: cb (225-288), b (0-63) 0x15 6 stdlevcr crr digital clamp levels ( selycrgb=0: cr, selycrgb=1: r) the 9-bit (0-511) crr video signals are clamped by the value determined assuming the center level (stdlevcr[5:0] + 225) for cr and the pede stal level (stdlevcr[5:0]) for r. setting range: cr (225-288), r (0-63) 0x16 6 dcline this sets the di gital clamp update unit. 0: 1v, 1: 1h (used for testing) 0x15 1 framedc [when the digital clamp update unit is 1v (dcline=0)] this register sets the number of update frames (framedc[4:0] + 1). setting range: 0-31 (1 to 32 frames) 0x17 5 tcdigclp this register sets the digital clamp time constant. 000: 1/1 001: 1/2 010: 1/4 011: 1/8 100: 1/16 101: 1/32 110: 1/64 111: 1/128 0x17 3 ? digital clamp specifications the 9-bit (0-511) video signals output from the adc are clamped at the set digital clamp pulse position to the set digital clamp level. the digital clamp level setting values are given below. y=118+stdlevy[5:0] cb/cr=225+(stdlevcb[5:0]/stdlevcr[5:0]) r, g, b=stdlevy[5:0]/stdlevcb[5:0]/stdlevcr[5:0] pedestal level setting value sink tip level pedestal level input signal sync level 511 0 digital clamp pulse digital clamp pulse
LC74950BG no.a1647-28/37 ? concerning the time constant setting a difference between the pedestal level of the 9-bit (0-511) video signals and set digital clamp level is obtained through digital clamp processing as shown in the figure be low. the result of multiplying this difference by the 1/x time constant is added to the input signals and output. in this way, the level is changed gradually to the set digital clamp level. the time constant is set using tcdigclp[2:0]. 8. gain 1) gain adjustments registers related to gain adjustments name functions sub address bit width selycrgb this register switches between ycbcr input and rgb input. 0: ycbcr, 1: rgb 0x14 1 syncon this register turns on and off the func tion to adjust the gain by cutting off the sync component of the digitally clamped y video signal for ycbcr input. this must be set to 0 for the rgb input (selycrgb=1). 0: on, 1: off 0x1b 1 cnline this register sets the nonlinear gain adjustment to on or off. 0: off (linear gain adjustment) 1: on (nonlinear gain adjustment) 0x19 1 coffset this register adjusts the nonlinear gai n region when the nonlinear gain adjustment is on (cnline=1). 0x1c 5 gainy linear gain adjustment (yg) the multipliers for linear gain adjustment are given below. y (selycrgb=0): (32+gainy[6:0])/64 g (selycrgb=1): (48+gainy[6:0])/64 0x19 7 gaincb linear gain adjustment (cbb) the multiplier is set to (48+gaincb[6:0])/64 for linear gain adjustment. 0x1a 7 gaincr linear gain adjustment (crr) the multiplier is set to (48+gaincr[6:0])/64 for linear gain adjustment. 0x1b 7 ? gain adjustment specifications the digitally clamped 9-bit video signals are converted into 8-bit video signals as shown in the figure below. in this case, the digital clamp level is shifted to the lsb of the 8 bits, and gain is adjusted in such a way that the components (video signals) above the digital clamp level fit in the 8-bit range. - pedestal level detection digital clamp level setting value input output 1/x 9 bits 8 bits
LC74950BG no.a1647-29/37 ? non-linear gain adjustment when cnline = 1, the output obtained in response to the input near the saturation region is made non-linear. when the non-linear gain adjustment parameter (conpara), obtain ed from the formula below, is less than the multiplier (rgb: (32 + gain_x[6:0])/64, ycbcr: (48 + 12a_gain_x[6:0 ])/64) that is used when the non-linear gain is adjusted, the input is multiplied by the non-linear gain adjustment parameter, resulting in a non-linear output. the non-linear start position and maximum non-linear out put value can be adjusted using coffset[4:0]. conpara = (1023 ? 9-bit video signals) (64 + coffset[4:0])/64 the figure below shows the gain adjustment output when the input is y and gain_y[6:0] = 63. 2) dc level adjustment registers related to dc level adjustment name functions sub address bit width selycrgb this register switches be tween the ycbcr input and rgb input. 0: ycbcr, 1: rgb 0x14 1 bradj this register adjusts the dc level. wh en the gain adjustment + dc level adjustment output is linear (bnline = 0), bradj is offs et from the video signals produced after the gain adjustment (the y signal is further offset by 64). setting range: -64 to +63, default value: 0 (40h) 0x1d 7 cnline this register sets the applicable non-linear gain adjustment, when the gain adjustment + dc level adjustment is used (bradj<40h), to on or off. 0: off (linear gain adjustment) 1: on (non-linear gain adjustment) 0x19 1 bnline this register sets the applicable non-linear gain adjustment, when the gain adjustment + dc level adjustment is used (bradj>40h), to on or off. 0: off (linear gain adjustment) 1: on (nonlinear gain adjustment) 0x1a 1 coffset this register adjusts the non-linear gai n region when the non-linear gain adjustment is on (bnline = 1) 0x1c 5 gain_y=63 (amp=1.73) 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 input(lsb) output(lsb) input cnline=0 cnline=1, coffset=0 cnline=1, coffset=4 cnline=1, coffset=8 cnline=1, coffset=12 cnline=1, coffset=15 cnline=1, coffset=20
LC74950BG no.a1647-30/37 ? dc level adjustment specifications the dc level is adjusted by adding bradj[6:0] to the y signal or rgb signals subjected to gain adjustment processing. ? non-linear gain adjustment + dc level adjustment when cnline = 1 and bradj[6:0]<0x40 (minus), the output corresponding to the input near the saturation region is made non-linear. when the non-linear gain adjustment parameter (conpara) obtained from the formula below is less than the multiplier (rgb: (32 + gain_x[6:0])/64, ycbcr: (48 + gain_x[6:0])/64) that is used when the linear gain is adjusted, the input is multiplied by the non-linear gain adjustment parameter, resulting in a non-linear output. the non-linear start position and maximum non-linear output value can be adjusted using coffset[4:0]. conpara = (1023 ? 9-bit video signal) (64 + coffset[4:0])/64 ? bradj[6:0]/2 similarly, when bnline = 1 and bradj[6:0]>0x40 (plus), the output corresponding to the input near the saturation region is made non-linear. when the dc adjustment parameter (brpara), obtained from the formula below, is less than bradj[6:0], the extent to which the output is to be non-linear is adjusted by adding the dc adjustment parameter to the y signal or rgb signals subject ed to non-linear gain adjustment processing. brpara = (127 ? non-linear gain output/16) (64 + coffset[4:0])/64 the figure below shows the output obtained when the gain adjustment and dc level adjustment have been performed (when gain_y[6:0] = 63, coffset[4:0] = 8). gain_y=63 (amp=1.73) 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 input(lsb) output(lsb) input cnline=0 cnline=0, bnline=1, bradj=64 cnline=0, bnline=1, bradj=0 cnline=0, bnline=1, bradj=127 input signal digital clamp level output signal a mp dc level adjustment value gain adjustment
LC74950BG no.a1647-31/37 9. external interface i 2 c: 100khz mode is supported. the slave addr ess can be selected using the pin settings. slave address: 0x98, 0x9a 1) control specifications slave operations in the standard mode (100khz) are supported. these must be used for setting the internal registers and setting the internal status output and correction characteristics. the slave addresses ar e listed in the table below. two addresses can be selected using the i 2 csel pin. slave address: (i 2 csel=0) slave address: (i 2 csel=1) 2) control and timing specifications (1) receive mode as shown below, the slave address w, sub-address and in put data must be set in this sequence after the start condition. the data of each sub-address can be input in auto address increments consecutively from the data of the sub-address specified. the data must be set consecutively with ack between one data and the next. the stop condition must be set last. parameter symbol min max unit scl clock frequency f scl 0 100 khz start condition hold time t h_s 4.0 s data hold time t h_d 0 s data setup time t s_d 250 ns sda and scl rise time t r 1000 ns sda and scl fall time t f 300 ns scl high level hold time t hi 4.0 s scl low level hold time t lo 4.7 s stop condition setup time t s_p 4.7 s sda scl slave address w sub-address input data t h_s t h_d t s_d t r t f t hi t lo t s_p 1 8 9 ack ack ack 1 0 0 1 1 0 0 r/w 1 0 0 1 1 0 1 r/w
LC74950BG no.a1647-32/37 (2) send mode as shown below, slave address w and the sub-address must be set after the start condition. the stop condition must be set last. slave address r must then be set after the start condition. the data of each su b-address is output in auto address increments consecutivel y from the data of the specified sub-address. the stop condition must be set last. (3) register settings the registers can be broadly divided into receive and send registers. receive registers are setting registers for internal control; send registers are for outputting the internal statuses to an external destination. the receive register settings can also be output to an external destination. sda scl slave address w sub-address ack ack sda scl slave address r input data input data ack ack ack
LC74950BG no.a1647-33/37 3) register map sub address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) initial value clock i/o control 00h r/w clkout2inv clkout1inv clkhsyiinv clkinininv clkadciinv clksel[2:0] 08h synchronous i/o control/o ffset adjustment control 01h r/w clkoutinv - - - hspllsel asyg[2:0] 88h 02h r/w vsoutinv ascrr[2:0] vsinv ascbb[2:0] 08h 03h r/w houtinv asvs[2:0] hsinv ashs[2:0] 08h h/v enable control 04h r/w hblks[11: 8] hblke[11: 8] 03h 05h r/w hblks[7:0] 7ah 06h r/w hblke[7:0] 4ah 07h r/w - vblks[10: 8] - vblke[10: 8] 01h 08h r/w vblks[7:0] 11h 09h r/w vblke[7:0] 02h digital clamp 0ah r/w dclpyon - dcpyset[5:0] a7h 0bh r/w dclpyv digclpon dclpyw[5:0] c4h 0ch r/w - dcpyvms[10: 8] - dcpyvme[10: 8] 01h 0dh r/w dcpyvms[7:0] 11h 0eh r/w dcpyvme[7:0] 02h 0fh r/w dclpcon - dcpcset[5:0] a7h 10h r/w dclpcv - dclpcw[5:0] 84h 11h r/w - dcpcvms[10: 8] - dcpcvme[10: 8] 01h 12h r/w dcpcvms[7:0] 11h 13h r/w dcpcvme[7:0] 02h 14h r/w selycrgb - stdlevy[5:0] a0h 15h r/w dcline - st dlevcb[5:0] 20h 16h r/w exsyncon - stdlevcr[5:0] 20h 17h r/w tcdigclp[2:0 ] framedc[4:0] 40h 18h r/w - - - 20h sub-contrast/brightness 19h r/w cnline gainy[6:0] 20h 1ah r/w bnline gaincb[6:0] 20h 1bh r/w syncon gaincr[6:0] 20h 1ch r/w - - - coffset[4:0] 08h 1dh r/w - bradj[6:0] 40h 1eh r/w - - 40h 1fh r/w - - - - - 00h 20h r/w - 00h afe/adc 21h r/w stbb - selfclpstbb_y stbb_y stbl_y[3:0] bfh 22h r/w ainsel - mainclplvcnt_y[1:0] - hpfclpon_y clplpfon_y gain_y 12h 23h r/w - - selfclpstbb_b stbb_b stbl_b[3:0] 3fh 24h r/w - - mainclplvcnt_b[1:0] - hpfclpon_b clplpfon_b gain_b 12h 25h r/w - - selfclpstbb_r stbb_r stbl_r[3:0] 3fh 26h r/w - - mainclplvcnt_r[1:0] - hpfclpon_r clplpfon_r gain_r 12h continued on next page.
LC74950BG no.a1647-34/37 continued from preceding page. sub address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) initial value pll 27h r/w corren - pllgain[2: 0] pllctl2 pllctl1 c0h 28h r/w hpldiv15 hpldiv14 hpldiv13 hpldiv 12 hpldiv11 hpldiv10 hpldiv9 hpldiv8 73h 29h r/w hpldiv7 hpldiv6 hpldiv5 hpldiv 4 hpldiv3 hpldiv2 hpldiv1 hpldiv0 58h 2ah r/w cpis_coast[3:0] cpis_org[3:0] aah 2bh r/w corrhss[11: 8] corrhse[11: 8] 02h 2ch r/w corrhss[7:0] 35h 2dh r/w corrhse[7:0] 1ch 2eh r/w osel[2:0] - - - 01h 2fh r/w - - - - - - - 06h 30h r/w - 00h 31h r/w - - - - - 80h 32h r/w - - 08h 33h r/w - - - 20h 34h r - - - - - - 00h 35h r - 00h 36h r - 00h 37h r/w - - 01h 38h r/w - - - - - - 00h 39h r/w - - - - icnt_y[2:0] 0ch 3ah r/w - - - - icnt_b[2:0] 0ch 3bh r/w - - - - icnt_r[2:0] 0ch 3ch r/w - - - - - - - - 00h 3dh r/w - - - - - - - - 00h 3eh r/w - - - - - - - - 00h 3fh r/w - - - - - - - - 92h pll and others 40h r/w - - clkindiv[5:0] 1fh feh r/w - - - - - - - - 80h
LC74950BG no.a1647-35/37 pdown complete power-down can be controlled using the pdwn pin. adc, pll and other items can be powered down individually by means of register settings. this makes it possible to limit the power consumption as required. internal states based on the pdwn pin setting pdwn adc pll logic communication remarks 0 powerdown powerdown clocks st opped stopped registers reset state 1 operating operating operating operating power down control by controlling registers item adc power-down can be controlled using dedicated r egisters. see below for the relevant registers. pll power-down can be controlled using dedicated r egisters. see below for the relevant registers. logic external input is selected and the external clock is stopped. similarly, the clock is stopped by selecting the pll mode and power down the pll circuit. output pin output-enable (hi-z) can be set by using the dedicated registers. communication cannot be stopped. name functions sub address bit width stbl_y stbl_b stbl_r these registers control the adc standby m ode (y: stbl_y, b: stbl_b, r: stbl_r). 0000: adc standby mode 1111: adc normal operating mode *1: any other setting than above inhibited. *2: these must be set in accordance with the operating mode of aec. 0x21 0x23 0x25 4 stbb this register controls the band gap vref circuit. 0: places the band gap vref circuit into the standby mode. 1: places the band gap vref circuit into the normal operating mode. *: this must be set in accordance with the operating mode of adc. 0x21 1 stbb_y stbb_b stbb_r these registers control the afe standby mode (y: stbb_y, b: stbb_b, r: stbb_r). 0: afe standby mode 1: afe normal operating mode *: these must be set in accordan ce with the operating mode of adc. 0x21 0x23 0x25 1 pllctl2 this register controls the h-lock pll power down mode 0: normal operating mode 1: h-lock pll power off 0x27 1
LC74950BG no.a1647-36/37 other (usage precautions) 1. precaution when turning on the power as shown in the figure below, start the transfer of the i 2 c bus command after factoring in the power-on time (a), pdwn operation time (b), reset operation time (c) and command transfer start time (d). a: power-on time this is the time taken from power-on to when the *v dd 15 operating supply voltage has reached the lowest level (1.35v) and operation has stabilized. th e power-on-time depends on the charact eristics of the power ics and other components, so it must be checked separately. with regard to *v dd 33 and *v dd 15, *v dd 15 must be turned on after *v dd 33 has turned on. b: pdwn operation time this is the time during which the "l" level must be applied continuously for a period of 10ms or more to the pdwn pin after the lowest level (1.35v) of the *v dd 15 operating supply voltage has been reached and operation has stabilized. c: reset operation time this is the time during which the "l" level must be applied continuously for a period of 10ms or more to the reset pin after the pdwn is released ("h" level). d: command transfer start time at least an interval of 10ms is require d from the time the reset pin is released ("h" level) to the start of command transfer. 1.35v 0.2v dd 2v 0.75v dd 3.0v dv dd 33 av dd 33 dv dd 15 av dd 15 pdwn command 0.2v dd 2v reset a b c d
LC74950BG no.a1647-37/37 2. precaution when turning off the power as a basic rule, power-off must be performed in the reverse sequence of power-on. however, no problems are posed if there is no wait time. a: power-off time this is the time it takes to reach the i o supply voltage and for operation to stabilize from the lowest level (1.35v) of the *v dd 15 operating supply voltage. with regard to *v dd 33 and *v dd 15, *v dd 33 must be turned off after *v dd 15 has been turned off or they must be turned off at the same time. ps this catalog provides information as of march, 2010. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that co uld endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention cir cuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other r ights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export contro l laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any i nformation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. a 3.0v dv dd 33 av dd 33 1.35v dv dd 15 av dd 15

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